Senior Design Verification Engineer

Design Verification Engineer

The Industrial Group is currently seeking a motivated Design Verification Engineer for the IC development of new products. Products in this strategy are comprised of integrated high speed and precision signal chains targeted towards Industrial applications. Product designs utilize advanced internal BiCMOS processes as well as standard fine line CMOS processes. These designs are then combined on a laminate package to provide a custom SIP (System In a Package) solution otherwise known as a chiplet.

The candidate's responsibilities will include system level verification of the products including simulation of digital and mixed signal circuits including high speed drivers and receivers, DACs, SPI/JTAG/SerDes interfaces, calibration routines and digital controls. This is a multi-die verification effort utilizing both Verilog and spice simulators. A Verification plan will be created at the product start determining the verification methods to be utilized and the block model plans. Duties also include working with evaluation engineers to compare and contrast simulation and lab results. The ideal candidate is a self-motivated individual and fast learner with strong technical, analytical and communication skills. The candidate will have the opportunity to learn system level design experience, work with newly developed internal BiCMOS processes and collaborate closely with an experienced development team.

Job responsibilities will include, but are not limited to, the following:

• Develop test bench environments and directed functional, random, and constrained random tests. Implement coverage driven verification methodologies. Create functional coverage metrics. Ensure these environments allow verification, design, product, and test engineers to efficiently develop functional test cases.
• Define and develop block level modeling and verification strategies based on design requirements and architecture
• Specify, and perform as necessary, block and chip level RTL, gate, and mixed signal co-simulation regressions. Track progress against verification plan
• Work with designers and product/apps engineers to achieve functional coverage goals and to debug the design and environment
• Work closely with evaluation engineers when silicon arrives to compare and contrast simulation results
• Participate in project meetings

Qualifications:

• Minimum requirement of BSEE, MSEE and 3+ years experience preferred
• Knowledge of System Verilog, UVM and OOP
• Knowledge of Verilog and Spice simulators
• Knowledge of Analog circuits and CAD tools (Cadence Virtuoso).
• Knowledge of a scripting language such as Python, TCL, Perl, Bash.
• Ability to problem solve at the circuit and system level
• Good presentation and writing/communication skills.
• Ability to collaborate in a team environment and across organizations

The expected wage range for a new hire into this position is $108,800 to $149,600. Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors. This position qualifies for a discretionary performance-based bonus which is based on personal and company factors. This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.