Senior/lead FPGA Silicon Design Engineer

Senior/Lead Fpga Silicon Design Engineer

Altera is seeking highly skilled Senior/Lead FPGA Silicon Design Engineer to ensure the excellence of next-generation Ethernet/Transceiver/Crypto for top-tier FPGAs. This role offers opportunity to make a significant impact at a tech-driven company that provides leading programmable solutions, easily deployable in applications ranging from embedded, industrial, & cloud to edge, unlocking limitless possibilities.

Responsibilities:

• Develop Micro-architecture and Design implementation for Ethernet/ Transceiver/Crypto IPs and subsystems.
• Work closely with the Architects to come up with an optimal design, RTL code development, involvement in pre-silicon and post-silicon debug, and own all the frontend collaterals for the IP/subsystem including STA, SDC, Timing constraints, CDC, Lint etc.

Qualifications:

• Candidates with 8-18 years of experience in silicon design, with a strong background in IP, SoC, or ASIC design and development & prior FPGA usage knowledge can excel.
• Expertise in RTL coding. Experience with UPF for power intent specification. Hands-on involvement in tape-in/tape-out processes and ECOs.
• FPGA silicon design involves close interactions/collaboration with Quartus software, IP, Validation & customer-facing teams across different geographical sites. Candidate is expected to participate/lead in cross functional collaboration, and mentoring junior team members.

Job Type: Regular

Shift: Shift 1 (India)

Primary Location: Bengaluru, Karnataka, India

Additional Locations:

Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.