Senior FPGA IP Solutions Engineer

Senior FPGA IP Solutions Engineer

Altera's Software, IP, and Solutions (SIPS) Group includes global engineering teams delivering world class embedded systems and solutions that includes HW and SW components that are tightly integrated and easy to use.

As a Senior FPGA IP Solutions Engineer, you will work closely with both HW and SW engineering teams to deliver foundational design components, released through Quartus, that are essential for Altera's embedded solutions and configuration systems. You will be solving challenging design problems requiring knowledge of embedded systems, IP design, SW layers and customer use cases. You will also be developing design examples and simulation models, accompanied by a rich set of technical documentation.

Your responsibilities will include, but are not limited to the following:

• Definition and design implementation of proprietary and industry standard specifications used in embedded systems and Altera's configuration flows.
• Functional design verification spanning IP, system, as well as HW-level testing. This includes creating verification test plans, simulation models, test execution and testbench improvements.
• Driving innovation, methodology and process improvements in design and verification activities.
• Technical customer support including sighting debugging.

The ideal candidate should possess the following traits:

• Driven to learn, and able to adapt to fast changing environments.
• A problem solver, inquisitive, and pays attention to details.
• Clear communicator, both written and verbal.
• Has a growth mindset, willing mentor, and team player.

The candidate should possess the following educational and work experience:

• B. Eng in Electrical Engineering, Computer Engineering, Electronics Engineering, or a related field with 7+ years of relevant industry experience.
• Familiarity with RTL, logic design or soft IP development.
• Experience with design verification, software programming or scripting languages (e.g. Perl, TCL, Python).
• Experience working across functional teams in a dynamic and global setting.
• Familiarity with industry-standard EDA tools and design methodologies.

The following qualifications are a bonus:

• FPGA design experience.
• UVM/OVM fluency.
• Experienced with guiding and coaching teams.

Job Type: Regular

Shift: Shift 1 (Malaysia)

Primary Location: Penang 15, Penang, Malaysia

Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.