Job Details:

Job Description:

leading supplier of FPGA embedded gigabit SERDES (PHY) ranging in operation from 1Gbps to 224Gbps, our team is looking for a qualified individual to join the SERDES design team.

The candidate will be joining a highly powered mixed-signal design team responsible for state of the art SerDes analog design, signal integrity, modeling, and electrical characterization.

Each designer is responsible for the functionality and quality of their designs and insuring that they work correctly in the overall system.

The candidate should have expertise in some (or preferably all) of the following areas:

• Very high speed analog design
• Very high speed custom digital design
• Ultra-low jitter clocking design
• SerDes architectures and modeling

Committed to team success, first time right quality, and ease of use is also important.

Specific duties could include, but are not limited to, designing complex, high performance analog & custom mixed-signal circuits, modeling (verilog, veriloga, Matlab, Py), simulation (verilog, spice, and mixed-mode), validation, optimization, documentation, layout and debug of such devices in most advanced process technologies.

Work Location: This position offers flexibility in work location. The selected candidate may choose to work from any of our sites: Jerusalem, Haifa, or Kiryat Ono .

Qualifications:

• Bachelor/Master/PhD in EE
• 8+ years of Experience with high performance FET-level analog and mixed-signal design.
• Experience with state of the art CMOS SerDes design techniques, circuits and approaches (ADC, TX, AFE, PLL knowledge is an advantage)
• Strong communication and teamwork skills

Job Type:

Shift:

Primary Location:

Additional Locations:

Posting Statement: