Graduate Talent - SOC FCT Design Engineer
Altera
Job Title
Successful candidate will be involved in all aspects of STA.
Candidate needs to work with Frontend, DFT and verification team to understand design definition and requirement and provide feedback on timing and physical challenges.
As a FPGA FC Timing design engineer candidate will be responsible for timing closure and signoff of FPGA/SoC and Subsystem timing.
Candidate will be involved in static timing analysis, providing/deriving interface timing constraints to partitions and doing final timing signoff.
Candidate will also work closely with design and architecture team for timing convergence analysis and will also work with physical design team for timing closure.
BE/MS/Phd in Electronics/Electrical Engineering with keen interest in physical design, timing and physical integration.
Candidate should be strong in communication, problem solving, analytical skill and attitude to learn and perform.
Contract Employee (Fixed Term)
Shift 1 (Malaysia)
Primary Location: Penang 15, Penang, Malaysia
Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.