Job Details:

Job Description:

Altera's IP Systems and Solutions Engineering (IPSS) team develops comprehensive solutions to provide customers easy and efficient access to the capabilities of Altera FPGA devices. These solutions are provided as highly configurable intellectual-property (IP) cores that are fully integrated with Altera's software CAD tool, Quartus Prime. External memory interfaces (EMIF) such as DDR5/LP5, Mobile Industry Processor Interface (MIPI) PHY solutions such as MIPI-DPHY/MIPI-CPHY, and high-speed source-synchronous IO interfaces are an important category for such IP cores. Applications such as AI, video processing, networking, storage and chip-to-chip communication make such IP cores a necessary component of any modern electronic system.

As an FPGA IP Design Engineer, you will work with a team of engineers to develop and verify state-of-the-art IP cores for memory and high-speed IO and video interfaces. You will be solving challenging design problems requiring system level knowledge of Silicon IC design, software, IP, and customer applications. You will be working on leading-edge device architectures, design definition, implementation, and verification. You will also be developing design examples and simulation models, accompanied by a rich set of technical documentation.

Your specific responsibilities will include, but are not limited to the following:

• Architecture and Design based on the latest protocol specifications for memory, high-speed IO and video/camera interfaces

• Device support and CAD tool integration

• Verification (e.g. verification IP, methodologies, frameworks, bus functional models, regression tests)

• Hardware power-on and debug

• New product release and rollout support

• Customer technical support

The candidate should possess the following behavioral traits:

• Strong skills in communication, initiative, innovation, and teamwork

• Highly motivated to learn and adapt to fast-changing technologies and environments

• Excellent problem-solving skills and attention to detail

• Demonstrate fundamental values such as accountability, integrity, and a winning mindset

• Collaborative mindset, strong influencing skills, and a willingness to work across geographical locations.

Our compensation is designed to reflect the Canadian labour market. The actual salary offered may vary based on several factors, including the position's location, as well as the candidate's experience, skills, training, and job-specific knowledge. In addition to base salary, we offer performance-based incentive opportunities that reward both individual contributions and overall company success.​

Estimated Salary Range: $105.0k – $115.0k CAD​

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We use artificial intelligence to screen, assess, or select applicants for the position.​ This posting is for an existing vacancy.​ Canadian work experience is not required for this role.

Qualifications:

Minimum Qualifications:

• BS degree or MS degree in Computer Engineering, Engineering Science, Electrical Engineering, Computer Science or equivalent, with 1+ year of experience or Master's Degree in related field

• 3+ months of experience in Digital logic hardware (e.g. SystemVerilog, Verilog and/or VHDL) design or verification

• 3+ months of experience in Software programming or scripting (e.g. C/C++ and/or Python)

Preferred Qualifications:

• 1+ year of experience with IP Integration, RTL Design, SystemVerilog, Verilog and/or VHDL

• 1+ year of experience with software programming and/or scripting languages (e.g. C/C++ and/or Python)

• FPGA design experience

• Experience with RTL simulation, static timing analysis, and timing closure

• Experience with Memory and video protocols

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