Principal /senior Principal Research Engineer (lead, 2.5D TSV Interposer & CPO Integration), HI, IME

Principal /Senior Principal Research Engineer

We are seeking a results-oriented leader for platform technology integration in Advanced Packaging department developing system-in-package at wafer level. The candidate will be responsible for defining the medium-to-long term process capability roadmap to support packaging platform technologies, developing 2.5D TSV interposers, and integrating optics with electronics using highly scaled u-bump and hybrid bond technologies for networking and high-performance computing interconnects.

Key Responsibilities:

• Evaluate industry trends and define differentiated platform technology architectures to obtain competitive advantage.
• Define simplest process flow with minimum number of process steps to realise platform technology architectures at lowest cost.
• Identify technology gaps and weak links with clear specifications for process module and make process module accountable for timely delivery.
• Realize platform architectures by closely working with a team of designers, integrators, process module and fab.
• Engage industry customers from proof of concept to low volume prototyping/manufacturing.
• Act as a project leader for industry, consortium, and internal core capability projects.
• Act as an influencer in internal leadership and industry collaborations.
• Build, mentor, and retain a high-performing team to deliver impact.
• Foster a culture of agility, technical excellence, individual and team innovation, intra-/inter-department collaboration, and continuous improvement.
• Effectively manage research funding obtained through grant proposals, industry partnerships, and strategic collaborations.
• Able to manage resource allocation efficiently amid competing priorities.
• Establish clear goals, metrics, and milestones to evaluate progress on technology development initiatives.
• Ensure effective project management, documentation, and knowledge dissemination across multidisciplinary teams.

Min Qualifications:

• Bachelor’s degree in Electrical Engineering, Materials Science, Chemical Engineering, Physics, Mechanical Engineering, or a related field.
• 15 years of experience in semiconductor industry, with expertise in Cu backend integration and exposure to advanced packaging technologies and managing projects and teams.
• Broad knowledge of multiple process technologies including lithography, etch, diffusion/thin films, electroplating, CMP, bonding.
• Strong understanding of considerations in process development cycle including early pathfinding and manufacturing scalability.
• Strong, hands-on people manager demonstrating excellent leadership, communication, and strategic thinking skills.
• Extensive experience working in a diverse, matrixed environment and collaborating across functions.

The above eligibility criteria are not exhaustive. A*STAR may include additional selection criteria based on its prevailing recruitment policies. These policies may be amended from time to time without notice. We regret that only shortlisted candidates will be notified.