Staff Silicon Design Engineer - Serdes PHY Designs

What You Do At Amd Changes Everything

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

The Role

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD's graphics processor IP, resulting in no bugs in the final design.

The Person

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

Key Responsibilities

This engineer will work on high-speed multi-gigabit SerDes PHY designs. This includes automated synthesis and timing driven place and route of RTL blocks for high speed Datapath and control logic applications, automated design flows for clock tree synthesis, clock and power gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. You will also support floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery.

Preferred Experience

Major in EE, CS or related, master's degree with 6+ years or Bachelor with 8+ years working experience, preferably with high speed multi-gigabit SerDes PHY designs or other high performance IP designs. Proficiency in Python and/or Perl is required. Additional languages are a plus. Versatility with scripts to automate design flow, and quality checks. Experience in automated synthesis and timing driven place and route of RTL blocks (Verilog experience preferred) for high speed Datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Strong background in digital circuit techniques, efficient and robust implementation topologies for logic functions, logic optimization, and transistor level circuit topologies for high speed, low power applications. Experience in floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery. Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation.

Academic Credentials

Bachelors or Masters degree in computer engineering/Electrical Engineering.

Location

Penang, Malaysia