Staff Physical Design Engineer (rtlpd)

Join Us At AMD

What you do at AMD changes everything. At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming, and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity, and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

The Role

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD's graphics processor IP, resulting in no bugs in the final design.

The Person

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

Key Responsibilities

• Collaborate with architects, designers, flow team, and PD team to achieve area and power targets, timing closure, and routability.
• Work on the physical implementation of the designs, including synthesis, floorplanning, and achieve routability.
• Optimize the design for performance, power, and area.
• Develop scripts and automation to streamline the design process.
• Debug timing failures to determine the root cause; work with RTL engineers to resolve design issues and achieve timing closure.
• Review congestion and propose improvement suggestions to fix the issues.
• Floorplan planning and fine tuning including IO and macro placement. IO and timing constraints.

Preferred Experience

Proficient in synthesis flow and tools, and optimization techniques. Proficient in debugging timing issues and congestion. Proficient in PnR flow and tools. Good understanding of Verilog and System Verilog language. Graphics Pipeline knowledge. Automating workflows in a distributed compute environment. Good understanding and hands-on experience in scripting: TCL, Perl, Makefile, shell, Python. ECO implementation knowledge would be an advantage.

Academic Credentials

Bachelors or Masters degree in computer engineering/Electrical Engineering

Location

Sydney, Australia