Sr. Silicon Design Engineer

AMD DACC Architecture/RTL Engineer

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

The role:

AMD DACC team delivers industry leading high-performance data copy and transformation accelerator that would be used for all AMD Server and Data Center products. It is targeting high-performance storage, networking, persistent memory, and various data processing applications.

The goal of the DACC is to provide higher overall system performance for data mover and transformation operations, while freeing up CPU cycles for higher level functions. The DACC IP is owned by China team from architect, design, verification, synthesis, validation and customer support.

As a DACC Architecture/RTL Engineer, you will have an outstanding opportunity to craft a functional unit in AMD's next-generation Server and Data Center. You will work as part of an experienced, skilled, and motivated engineering team with a track record of success. You will help make AMD's ambitious future CPU/GPU roadmap a reality while working in a highly collaborative environment at the cutting edge of technology.

The person:

Candidate will work as architecture/RTL design engineer for the DACC IP development. Candidates need to have solid IP design background and outstanding global communication skill.

Key responsibilities:

• Drive and own the IP roadmap and specifications for Data Accelerator
• Collaborate with a team of hardware, firmware and software engineers to define the high-level architecture.
• Participate in the definition of microarchitecture of next-generation Data Accelerator.
• Contribute to design verification, synthesis, power reduction, timing convergence, and floorplan efforts
• Execute on RTL design and coding for various blocks of DACC core and related logic.
• Short term global travel upon business need

Preferred experience:

• Global company working experience, fluent oral English
• RTL coding experience for high-performance DMA/RDMA engine
• Power-saving techniques
• Awareness of synthesis, place and route, and timing closure concepts
• Development experience from clean-sheet design to product tape-out to post-silicon debug
• Proven experience with microarchitecture development, as demonstrated by patents, publications, product features
• Strong problem-solving and debugging skills

Academic credentials:

• MSEE within 2-5 years, or BSEE within 4-7 years' experience in digital ASIC/SOC design.

Location: Shanghai