SOC Verification Engineer: SOC DDR, UMC

Mts Silicon Design Engineer

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The Role (SOC Verification Engineer: SOC DDR, UMC):

Work on SOC level verification activities, the person will be responsible for bringup verification of LPDDR5, UMC at SOC. Work with testbench team to bringup required infrastructure to bring up testbench and simulation. He will be responsible to coordinate with Design team for RTL delivery, work with design (IP, Subsystem, SOC) for RTL and TB collaterals and resolve issues. He should have good understanding of LPDDR5, UMC. He will be responsible to create TB collaterals for LPDDR5, UMC and phy bringup.

The Person:

Engineer with strong self-driving ability. Need excellent communication skills (both written and oral). Strong problem-solving skills, go to person for SOC testbench, DDR verification, C/C++ Coding, UVM coding, Testcase coding, checkers and assertions.

Key Responsibilities:

• DDR Simulation bringup (Has responsibility of TB, Testcase, coordination between design and dv team)
• Memory verification is key responsibility.
• Work with Memory architects to resolve issues seen in simulation.

Preferred Experience:

Good understanding of LPDDR*, UMC, Nandflash, Nor Flash etc… Expertise in IP, Subsystem and SOC Verification with specialization in NLP Simulation. Strong hands-on experience in different SOC Verification activities, DDR Simulation, UVM, System Verilog, X86, C++, HW/SW co-verification, Scripting (phython) Test plan review, Debug/triage, Coverage, Strong Problem Solving, Automation and Debugging Skills, System bus protocol understanding including some of the common IPs like ACE, CHI, AXI, PCIe, DDR, memory controller etc. Comfortable with design/verification tools and flows like VCS, Verdi, SOC Connectivity, SV assertions, HW-SW co-simulations, UPF/CPF flows etc. Strong understanding of System integration, Make file flow, Verification Methodologies, Boot up sequence. JIRA based project management is a plus.

Academic Credentials:

BE/B.Tech/ME/MTECH/MS or equivalent in ECE/EEE/CSE 8-12 years of strong DV experience in CLK, RST verification, NLP simulation, IP, Sub System & SOC Verification.