Silicon Design Engineer

Join Us At AMD

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

The Role

Central DFX (CDFX) is a centralized ASIC design group within AMD's Technology and Engineering organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. It is also responsible for DFx design methodology and CAD automation tools development to support the global DFX engineering teams across AMD.

The Person

As a DFx Silicon Design Engineer, you will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives. This role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team!

Key Responsibilities

Primary Responsibility:

• Develop RTL for ASIC design-for-test (DFT) features as per architectural or design flow automation specifications
• Perform RTL design integration, insertion, synthesis, equivalency checking, timing analysis and closure including defining constraints
• Develop scan compression insertion and stitching flow automation
• Perform scan ATPG/DRC verification, pattern generation and simulation
• Deliver production quality ATPG patterns to product engineering team, and provide pattern bring-up support on first silicon

The successful candidate may also be responsible of:

• Debugging and verifying block-/chip-level DFT/DFX features
• Porting or creating the DFT/DFX verification environment
• Block/chip test plan creation and development
• Stimulus writing and debug, and regression clean-up

Preferred Experience

Good understanding of computing/graphics design architecture

Familiar with ASIC design, fabrication, assembly and ATE test

Knowledge of DFT techniques such as JTAG/IEEE standards, Scan and ATPG, memory BIST/repair or Logic BIST is a plus

Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl)

Familiar with verilog design language, Verilog simulator and waveform debugging tools

Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus

Strong problem solving skills

Team player with strong communication skills

Academic Credentials

Bachelors or Masters degree in computer engineering/Electrical Engineering

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.