Senior Silicon Design Engineer

Join Us At Amd

What you do at AMD changes everything. At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

The Role

We are seeking a motivated DFx engineer to join our SBIO design team. In this role, you will contribute to the next generation of AMD's silicon innovation while developing your expertise in DFx methodologies and advanced design practices. You will be part of a forward-thinking engineering organization that values learning, encourages fresh ideas, and empowers emerging talent to grow into impactful contributors who help shape the future of semiconductor technology.

The Person

You have a passion for modern and advanced DFx design and techniques. You are a team player with excellent communication skills and experience collaborating with engineers located across different sites and time zones. You have strong analytical and problem-solving skills, are willing to learn, and are ready to take on challenges.

Key Responsibilities

Implement and verify DFT features such as SCAN, MBIST, and BSCAN. Perform Spyglass DFT bring-up, debug and coverage improvement. Perform scan insertion and ATPG (Traditional, Cell Aware, SSN) pattern generation. Verify ATPG patterns using gate level simulation. Analyze and improve ATPG and DFT DV test coverage. Develop and debug DFT verification tests. Work with the Synthesis and PD team to ensure correct DFT implementation and timing closure. Provide post silicon support to ensure successful bring up.

Preferred Experience

Experience in scan stitching and strong knowledge of scan stitching concepts. Exposure to MBIST/BISR implementation and the Synopsys SMS MBIST insertion flow. Excellent hands on ATPG experience and familiarity with ATPG related file requirements. Knowledge or experience with Tessent SSN (Siemens) is a plus. Knowledge of Spyglass DFT. Good in C++ and object-oriented programming concepts. Familiarity with automation scripts such as Perl or Python is a plus. Understanding of JTAG and IJTAG fundamentals. Exposure to AI related work is a plus. Experience with post silicon bring up is a plus. Exposure to static timing analysis and timing closure is a plus.

Academic Credentials

Bachelors or Masters degree in computer engineering/Electrical Engineering.

Location

Penang, Malaysia