Principal Silicon Design Engineer

Join Us At AMD

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

The Role

The SOC RTG team develops leading edge discrete graphics SOCs. The team owns SOC execution and is actively engaged from architecture to production. Working as part of the SOC leadership team, candidates will gain knowledge in system and IP level design, SOC architecture and implementation strategies.

The Person

Excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. Highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team.

Key Responsibilities

• Integrate AMD internal IPs RTL/DV environments into SoC Debug function/performance of Graphics, Display, SMU IPs
• Engage with IP and SOC teams to drive closure to IP RTL deliverables
• Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation
• Drive design and methodology improvements across teams to improve overall program execution

Preferred Experience

Proficiency with Verilog/VHDL RTL design languages. Knowledge of chip bus interfaces such as AHB, AXI and various standard peripherals & interfaces is required. ASIC DV experience in reusable verification methodology such as UVM. Have hands-on experience in SOC Design/Integration activities, involving IPs, padring and pinmuxing. Have knowledge of SOC design specification, architecture and micro-architecture,ASIC, SOC, and IP Verification. Strong industry experience in Synthesis, Floor-planning, Placement, clock trees synthesis, Post Route Timing closure for high-speed designs. CDC, PTPX, STA, LINT & DFT, IP, Physical design flow & scripting in TCL, Python

Academic Credentials

Bachelor or Masters Degree in Electrical Engineering, Computer Engineering or Computer Science

Location

Santa Clara, CA