Physical Design Engineer

AMD Job Opportunity

What You Do At AMD Changes Everything At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

The Role

In this role, you will be responsible for the implementation and signoff of complex digital integrated circuits from RTL to GDSII, focusing on cutting-edge process technologies. You will work closely with frontend design, DFT, and CAD teams to achieve power, performance, and area (PPA) targets while ensuring schedule adherence.

The Person

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

Key Responsibilities

• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features
• RTL-to-GDSII Implementation – Execute full physical design flow including synthesis, floorplanning, placement, CTS, routing, and signoff.
• Timing & Power Closure – Perform static timing analysis (STA), power analysis, and optimize designs to meet timing, power, and area goals.
• Physical Verification – Run DRC, LVS, and other verification checks to ensure design manufacturability.
• Methodology & Automation – Develop and maintain scripts to improve design efficiency and quality.
• Cross-functional Collaboration – Work with frontend, DFT, and CAD teams to resolve design issues and implement methodology improvements.
• Documentation & Reporting – Create clear documentation and regularly report progress to project stakeholders.

Preferred Experience

Full chip floorplan experience. Scripting language experience: Perl, Tcl, Python. Exposure to leadership or mentorship is an asset Experience with high-performance CPU/GPU/AI accelerator physical design in advanced nodes (7nm and below). Hands-on experience with low-power design techniques (power gating, multi-voltage, DVFS) and UPF/CPF flow. Familiarity with 3D-IC or chiplet-based design methodologies and associated tool flows. Knowledge of package-aware floorplanning and system-level co-design considerations. Experience with machine learning applications in physical design (e.g., auto-placement, routing prediction). Prior exposure to design for testability (DFT) integration and post-silicon debug support. Proven track record of successful tape-outs in high-complexity SoC projects.

Academic Credentials

Bachelors or Masters degree in computer engineering/Electrical Engineering

Location: Beijing