Performance Verification Engineer

Performance Verification Engineer

What you do at AMD changes everything. At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

The role: As a silicon design engineer, you will work with performance architects and designers to verify performance metric KPIs and meeting product performance targets on SOC emulation.

The person: You have a passion for modern, complex processor architecture, digital design, and performance verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

Key responsibilities:

• Develop and execute performance workloads on emulation platforms to validate architecture, analyze system performance, and identify bottlenecks across hardware, firmware, and software.
• Develops and utilizes automation aids, flows, and scripts in support of better emulation utilization.
• Design new infrastructure and debug features to improve coverage, visibility, and debuggability across diverse performance use cases.
• Reproduce and root-cause performance issues in pre-silicon environments based on post-silicon observations, and drive fixes or model updates.
• Collaborate closely with design, architecture, performance/power, silicon validation, and software teams to validate complex architectural features and meet performance targets

Preferred experience: 3-4 years of experience on emulation based functional and performance verification for multimillion gate SoC designs. Should have strong exposure to RTL coding and SOC bring-up. Good debugging skills, experience of working with various debugging tools on RTL like Verdi, fsdb analysis. Good knowledge in C/C++, scripting (Python/Perl/Tcl) and ability to develop post-processing tools for stimulus generation and debug infrastructure. Experience with hardware performance counter monitoring tools. Exceptional foundation in systems architecture, cutting across multi-core systems, memory, storage and I/O subsystems.

Academic credentials: Bachelors or Masters degree in computer engineering/Electrical Engineering.