Lead IP / SOC Verification Engineer

SMTS Silicon Design Engineer

What you do at AMD changes everything. At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

The Role

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD's graphics processor IP, resulting in no bugs in the final design.

The Person

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

Key Responsibilities

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified

Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases

Estimate the time required to write the new feature tests and any required changes to the test environment

Build the directed and random verification tests

Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues

Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements

Preferred Experience

Proficient in IP, SoC level ASIC verification with 12+ yrs of experience

Proficient in debugging firmware and RTL code using simulation tools

Proficient in using UVM testbenches and working in Linux and Windows environments

Experienced with Verilog, System Verilog, C, and C++

Developing UVM based verification frameworks and testbenches, processes and flows

Automating workflows in a distributed compute environment.

Desirable experience with prior exposure on SoC/NoC Interconnects, High-Speed protocols like PCIe, USB3

Experience in SoC Performance verification or Performance modeling is a strong plus

Experience in DFx logic verification is a strong plus

Experience in Crypto IP verification at SoC level is a plus

Desired experience in DDR memory controller verification

Exposure to Synopsys VCS, Verdi tool features to aid in Code coverage, Fault coverage analysis is a plus

Excellent debugging skills in RTL and 0'delay Gate-level-simulations

Scripting language experience: Perl, Python, Makefile, shell preferred

Experience in SoC verification and usecases is a plus

Good understanding and hands-on experience in the UVM concepts and SystemVerilog language

Exposure to leadership or mentorship in leading teams is asset

Academic Credentials

Bachelors or Masters degree in computer engineering/Electrical Engineering