DFT DV Engineer

Join Us At Amd

What you do at AMD changes everything. At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

The Role

The S3 DFT team fully owns AMD S3BU (Strategic Silicon Solution Business Unit) SOC DFT definition, implementation, verification till final silicon bring up. We design the APUs mainly for consoles. Design Verification team is part of the whole chip design team and responsible to make sure the RTL quality. You will be working with DFT design and front-end team to verify the debug logic and make sure it is working on post-Si.

The Person

Has related knowledge for design verification and good debug skills. Familiar with entire ASIC design flow. Has good communication skills and be able to work both independently and in a team. Should have strong problem-solving skills.

Key Responsibilities

Qualified candidate will perform some or all functions below:

• Develop test plan according to the specification and review with Architect and Designer.
• Develop test scenarios to verify the design and analyze the coverage.
• Complete the verification task before TO.
• Participate in ATE bring-up and debug the DFT patterns on ATE.

Preferred Experience

Proficient in one kind of simulation tool like VCS, have good debug skill. Familiar with SystemVerilog/C/C++ language. Have the knowledge for UVM. Familiar with script language like SHELL/Perl/Python. It is better to have the DFT related knowledge like IEEE1149.1/6 for JTAG/BSCAN. Have Memory BIST knowledge is a plus. Have background knowledge of High-Speed IO(USB/PCIE/DDR/Display) is a plus. Familiar with the whole verification flow from test plan review to TO. Have experience for post-Si debug is a plus. Good written and spoken English.

Academic Credentials

Bachelor or Master, major in EE, CS or related area + 3 years working experience.

Location

Shanghai, Beijing