CPU Architecture And RTL Design Lead Engineer

What You Do At AMD Changes Everything

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

The Role

As a CPU Core CPU Architect/RTL Design Engineer, you will have an outstanding opportunity to drive the definition, implementation (RTL design), and integration of Clocking, Reset and Power in AMD's next-generation core. You will work as part of an experienced, skilled, and motivated engineering team with a track record of success. You will help make AMD's ambitious future CPU roadmap a reality while working in a highly collaborative environment at the cutting edge of technology.

The Person

You approach challenges relentlessly with both critical thinking and creativity. You work as part of a team with strong communication and collaboration skills. You have a proven understanding of modern CPU architecture and have ideas and/or drive to make it even better. Does this describe you? If so, then join us

Key Responsibilities

• Collaborate with a dedicated team of engineers to define and implement CPL microarchitecture for AMD CPUs.
• Reliably deliver a design from concept through tapeout by innovating through complex and challenging requirements.
• Drive design closure gaining experience with Static Timing, CDC/Gate CDC, and Static Power analysis.
• Identify customer challenges and insert a compelling AMD value proposition to address challenges.
• Make technical contributions and innovations that enable high performance, high frequency, and power efficiency on caches, fabrics, and interfaces of our server, desktop, and laptop CPUs.

Preferred Experience

• Proficiency with Verilog HDL, Clock/Power Domain Crossing concepts, and Power Management concepts.
• Understanding of modern CPU architecture - prior experience designing shared cache or last level cache and related IPs a plus.
• Eagerness to learn and grow as a CPL design engineer.
• Collaborate effectively towards the success of the project by working closely with logic design, physical design and verification teamates across the wider organization.
• Demonstrate a responsive track record of engaging with a diverse set of teams and across a broad set of technical areas to facilitate design delivery.

Academic Credentials

• Bachelors or Masters degree in computer engineering/Electrical Engineering