ASIC Design Verification Engineer

Join Amd's World-Class Verification Team

What You Do At AMD Changes Everything At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

The Role

AMD is looking for people like you to join their world class verification team delivering ASIC IP to address next generation networking and security applications. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

The Person

The ideal candidate will possess a problem-solving mindset, attention to detail and the curiosity to uncover hard to find issues.

Key Responsibilities

• Collaborate with the design team to determine testbench development strategies for pre-silicon validation of leading edge networking IP
• Identify reuse opportunities of TB components between simulation and emulation environments
• Provide C models for stimulus generation and prediction of various functions of the IP
• Promote and incorporate use of AI powered verification tools into daily development flow
• Identify methodology improvements to facilitate better horizontal and vertical reuse and shorter development time
• Propose strategies for faster coverage closure
• Offer mentorship to younger team members

Preferred Experience

Previous experience in ASIC/FPGA verification with a track record of successful tapeouts Extensive experience in designing and implementing self-checking testbenches, coverage closure techniques and regression management flows In depth knowledge of modern verification practices including UVM, Formal Verification and assertion based test Hands on experience using AI tools for design verification Experience and knowledge of communications standards (such as IEEE 802.3 Ethernet, Flex Ethernet, OTN, Interlaken, PCIe) Fluency in Verilog, System Verilog, C or C++ Excellent written and verbal communication skills Experience with VCS simulation tool, Perl/Shell scripting

Academic Credentials

Bachelors or Masters degree in Computer Engineering/Electrical Engineering/Computer Science

Location: Markham OR Ottawa Ontario CA #LI-DW1 #LI-HYBRID