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IC Package Design Engineer

Develop innovative flip-chip BGA solutions for high-speed ASIC applications
San Jose, California, United States
Senior
$141,000 – 226,000 USD / year
yesterday
Actalent

Actalent

A provider of engineering and sciences services and talent solutions for various industries.

IC Package Design Engineer – Flip-Chip BGA / High-Speed ASICs

Our client, a global leader in advanced semiconductor technologies, is seeking an experienced IC Package Design Engineer to support the development of complex flip-chip BGA packages for cutting-edge ASICs. This role is part of a world-class R&D team focused on delivering high-performance solutions for applications in artificial intelligence (AI), networking, high-performance computing (HPC), and 5G base stations.

Responsibilities

  • Design and develop advanced flip-chip BGA packages for high-performance ASICs
  • Support high-speed SerDes integration and power delivery requirements
  • Collaborate with global R&D teams to define package architecture and design rules
  • Contribute to design efficiency improvements and automation initiatives
  • Utilize Cadence APD for layout and design validation

Required Skills

  • Proven experience with flip-chip BGA package design
  • Strong understanding of high-speed SerDes, signal integrity, and power delivery
  • Proficiency in Cadence APD and related design tools
  • Background in ASIC packaging for high-performance applications

Preferred Qualifications

  • 1+ years of experience with Cadence scripting or similar design automation tools
  • Interest in developing and implementing design automation workflows

Pay and Benefits

The pay range for this position is $141000.00 - $226000.00/yr. This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Workplace Type

This is a fully onsite position in San Jose, CA.

Application Deadline

This position is anticipated to close on Sep 16, 2025.

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IC Package Design Engineer
San Jose, California, United States
$141,000 – 226,000 USD / year
Engineering
About Actalent
A provider of engineering and sciences services and talent solutions for various industries.