Formal Verification Engineer

Formal Verification Engineer

Ensure design correctness using mathematical methods like model checking and equivalence checking, without relying on simulation. Detect corner-case bugs early in the design cycle to improve quality and reduce verification time.

Minimum of 15 years of experience, with demonstrated experience in design verification on complex projects in a leading chipset company.

Roles & Responsibilities:

• Strong knowledge with ASIC simulation tool & verification languages: all sign-off simulators, waveform debugging tools like Simvision / Verdi
• Fluent in verification language such as UVM/OVM/RVM/System Verilog, Vera, Verilog
• Experience in writing test-plans and creating directed and random test cases
• Strong scripting skills in Perl, Python, shell etc.
• Strong problem-solving skill to quickly identify and provide solution under tight schedule pressure

Professional & Technical Skills:

• Experience in low power verification using UPF or AMS/DMS is a plus

Education: BE

Experience with verification of DSP based / RF designs at IP and / or subsystem level strongly preferred

15 years full time education

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