Formal Verification Engineer

Senior Digital Verification Engineer

Ensure design correctness using mathematical methods like model checking and equivalence checking, without relying on simulation. Detect corner-case bugs early in the design cycle to improve quality and reduce verification time.

Minimum three years of experience is required. Educational qualification: 15 years full time education.

We are seeking a highly skilled Senior Digital Verification Engineer with a minimum of four years of experience in UVM-based digital verification. The ideal candidate will have expertise in verifying AMBA protocols and core IPs, including DMA architectures with high throughput and complex descriptor structures. Candidates with a Master's degree from top Indian institutions (IIT, NIT, IIIT – top 20) are strongly preferred. Applicants should document their State entrance rank and GATE percentile as part of their qualifications.

Roles & Responsibilities:

• Develop and execute UVM-based verification environments for digital IPs, focusing on AMBA protocols and DMA engines.
• Design and implement testbenches to thoroughly verify complex descriptor structures such as linked lists and scatter/gather mechanisms.
• Analyze and debug verification failures, ensuring robust coverage and compliance with functional requirements.
• Collaborate with architecture, design, and firmware teams to define verification strategies and resolve issues.
• Document verification plans, test cases, and results; maintain clear and organized reporting.
• Contribute to the continuous improvement of verification methodologies and best practices.

Professional & Technical Skills:

• Minimum 4 years of hands-on experience in UVM digital verification.
• Strong background in AMBA protocols (AXI, AHB, APB) and core IP verification.
• Expertise in verifying DMA architectures capable of 5Gbps throughput.
• Proficient in handling complex data structures, including linked lists and scatter/gather descriptors.
• Solid understanding of digital design concepts, RTL, and simulation tools.
• Familiarity with scripting languages (e.g., Python, Perl) for automation and debugging.
• Excellent problem-solving and analytical skills.

Additional Information:

• Master's degree from IIT, NIT, IIIT (top 20 schools in India) is mandatory.
• Candidates must provide documentation of their State entrance rank and GATE percentile.
• Strong communication skills and ability to work effectively in a team-oriented environment.
• Prior experience in a fast-paced semiconductor or IP development environment is an advantage.